PCB Quality Issues That Affect Assembly
The design of a PCB and its manufacturing quality has a direct correlation with how well the board can be assembled. As not all PCB manufacturers are created equal, at times getting the least expensive per board may end up costing more in ruined boards and reputation with customers. When designing and purchasing boards, there are quite a few items to look for that can adversely affect how easily the boards can be put together.
Co-planarity of the PCB, also referred to as warp or twist, is a problem that affects most multilayer boards. A good PCB manufacturer will control heat increase rates and provide rigid support for the boards to ensure flatness during manufacturing. Alternately, they will alert the customer if the board has an “unbalanced” design that may cause warping during the process. The warp or twist is built in to the lamination cycle and is almost impossible to remove. To prevent this, some PCB manufactures will bake the panels in a 260 degree Fahrenheit oven with weights on top to flatten the boards, which does seem to help remove some of the built in lamination warp. The lamination cycle for multilayers causes the warp by unlocking the internal stress caused by etching the copper off of the laminate. As the press heats up the cores the laminate becomes more pliable, causing the etched copper to move back to its initial position and size.
Thickness accuracy across the PCB panel is helpful in assuring the tip of the pick and place, automatic glue machines and paste stencils can follow the top surface properly. During lamination, it is possible to have as much as 5 mils (127 micrometers) of thickness difference across a larger PCB.
Any significant indentations on the PCB surface will make it more difficult for the screen stencil to make proper contact with the surface, and may cause insufficient or excess solder to be screened in some areas. These indentations are sometimes due to multiple stacked internal layers with a similar cut out, creating a void of metal within the circuit board itself. This can leave either the top or bottom layer reflecting the inner layer copper openings.
To ensure the fine pitch chips’ pads match the PCB’s pads on the same plane, the scaling of the
outer layers becomes important. When a PCB is made, manufacturers adjust the size of each layer separately to get the final laminated positional tolerance of the pads and vias correct. A panel of PCBs will usually shrink after etching and expand during lamination, but the 18”x24” PCB panel does not expand linearly—there is a sweet spot in the middle that does not change position significantly. However, as you progress to the corner edges, the scaling (or true pad positioning) error changes more quickly. With the onset of laser direct imaging and laser ablated micro vias, the overall accuracy of any particular pad placement in relation to the tooling holes has greatly improved. When placing 0201 and 01005 chips or large BGAs, an accurate pad-to-fiducial measurement and true tooling hole positioning is important.
For BGA, LBGA and TBGA packages, the solder ball on the chip to PCB pad misalignment has to be less than 150 μm to assure a correct positional soldering process. This is achievable with a wide range of pick and place machines. On large PCBs, which suffer from a greater degree of positional tolerance, local fiducials close to larger devices can compensate a significant amount to null out PCB tolerances. During assembly, it is recommended to use local recognition capabilities of the placement system rather than only the outside centering marks. When providing boards to an assembly house, it is best to include these local fiducials to help them in the assembly. On designs that require high reliability, attention must be given to the shape of the traces connecting to the vias that exist within pads on the boards. Trace cracking has been observed during drop and bend tests of large-packaged components due to edge stress on the solder fillet. The trace cracking usually occurs at the edge of the solder mask opening around the pad because this is the highest stress point on the copper. To design around this failure mode, it is recommended that the trace under the solder mask edge is made wider than the rest of the trace. The trace width should be 50% of the total pad that it is connecting to and can taper down to the desired trace width started 10 mils from the pad.
Dual-row and three-row QFN packages with thermal pads are designed to provide superior thermal performance. While a thermal pad provides a good solderable surface, thermal vias are needed to provide a direct thermal path through to inner and bottom layers of the PCB to effectively increase the thermal spreading, thereby removing more heat. The number of vias needed will depend on the desired heat dissipation and application. One disadvantage of via-in-pad in a complex PCB is that without a barrier, the solder will wick into the vias and through the board during the reflow process, potentially reducing the solder connection and heat dissipation rate of the board. This can be eliminated by plugging or tenting the vias with solder mask or a via fill process during bare board manufacturing.
Surface smoothness of pads and via-in-pads is also very important. Most PCB manufacturers produce good quality ENIG (Electroless Nickel Immersion Gold) finishes, and it is the most used plating option as it offers the best finish for flatness and solderability. Newcomers such as ENEPIG (electroless nickel electroless palladium and immersion gold) combinations also have good quality finishes in regards to both flatness and solderability while still adhering to RoHS rules. When manufacturing via-in-pad, even if the vias are plugged or filled, it is a hard to get the pad totally flat without some sign of a dimple on the surface of the pad. Any pad with a significantly sized dimple can give the assembly house problems in soldering, particularly with leadless parts such as BGAs. ENIG contamination, sometimes called black pad syndrome, is extremely difficult to solder, as the impurities act as a barrier between the pad and solder. Subsequent testing will show decreased pull strength, even if the part looks like it soldered properly, as the underlying issue exists within the assembly and cannot be seen externally.
Issues with soldermask can also be problematic. Smoothness is important, but ensuring there is no encroachment onto any pads will ensure good solder joints during assembly. Likewise, ensuring that soldermask properly meets the edge of each pad will ensure there is no exposed copper. Exposed copper will cause the bare boards to pass electrical testing at the board manufacturer, but once solder is used to place components, it may touch the exposed copper and cause a short.
When designing and ordering your PCBs, there are many variations and problems that can occur during the manufacturing process. By proactively designing to avoid these issues, and carefully selecting a high quality manufacturer, you can ensure the highest number of boards will be ready for assembly.